Generally, in semiconductor devices incorporating a reference voltage generation circuit, manufacturing variations in threshold values Vth of respective transistors, resistance values of respective resistance elements, and the like included in the reference voltage generation circuit can cause a reference voltage Vref assumed in design to vary significantly from a desired value. Thus, semiconductor devices requiring a stable reference voltage Vref require a highly precise reference voltage generation circuit. To correct reference voltage variation in the reference voltage generation circuit caused due to manufacturing variations, semiconductor devices incorporate many auxiliary transistors for adjusting a reference voltage by correcting a wiring layer or are configured such that the reference voltage can be adjusted by a laser trimmer after manufacturing. However, correcting the reference voltage variation in the reference voltage generation circuit by such configurations leads to problems such as an increase in a layout area of the reference voltage generation circuit and an increase in the number of steps for performing voltage adjustment. Accordingly, to solve such problems, various reference voltage generation circuits have been proposed.
JP 04-65546 B2 discloses an ordinary reference voltage generation circuit. JP 04-65546 B2 proposes a reference voltage generation circuit having a structure in which, by using constant current characteristics of a depletion type MOSFET (metal oxide film semiconductor field-effect transistor) having a gate G and a source region S connected to each other, a voltage generated in an enhancement type MOSFET that has a gate G and a drain region D connected to each other and operates at the constant current is used as a reference voltage Vref.
FIG. 58 illustrates an ordinary reference voltage generation circuit 100. The reference voltage generation circuit 100 includes a depletion type MOSFET (hereinafter referred to as “depletion type transistor”) Md and an enhancement type MOSFET (hereinafter referred to as “enhancement type transistor”) Me that are connected in series. The gate G and the source region S of the depletion type transistor Md are connected to each other. The gate G and the drain region D of the enhancement type transistor are connected to each other. Furthermore, the gate G and the source region S of the depletion type transistor are connected to the gate G and the drain region D of the enhancement type transistor. Additionally, a high voltage supply terminal Vdd is provided at a drain region D of the depletion type transistor Md, and a low voltage supply terminal Vss is provided at a source region S of the enhancement type transistor Me. In addition, a voltage output terminal OUT is provided at a connection point between the depletion type transistor Md and the enhancement type transistor Me. In the reference voltage generation circuit 100, both the depletion type transistor Md and the enhancement type transistor Me are of N-channel type. It should be noted that the depletion and enhancement types are classified by a relationship between gate voltage and drain current. In the depletion type, when no gate voltage is applied to the gate, there exits a channel, through which drain current flows. On the other hand, in the enhancement type, without any gate voltage applied to the gate, no channel exists, and therefore no drain current flows.
FIG. 59 illustrates one example of current/voltage characteristics of the depletion type transistor Md and the enhancement type transistor Me included in the reference voltage generation circuit 100. The horizontal axis represents gate-source voltage Vgs between the gate G and the source region S, and the vertical axis represents drain current Ids. In the depletion type transistor Md, since the gate-source voltage Vgs is fixed at 0V, drain current as a constant current Iconst flows as long as the drain-source voltage between the drain region D and the source region S is in a saturation region. The drain current as the constant current Iconst also flows to the enhancement type transistor Me connected in series to the depletion type transistor Md. Accordingly, the gate-and-source voltage Vgs of the enhancement type transistor Me in which Ids=Iconst can be taken out as a reference voltage Vref from the voltage output terminal OUT.
When Vth_d represents a threshold voltage of the depletion type transistor Md and Vth_e represents a threshold voltage of the enhancement type transistor Me, the reference voltage Vref can be represented as a sum of an absolute value of the threshold voltage Vth_d and an absolute value of the threshold voltage Vth_e, i.e., “Vref =|Vth_d|+|Vth_eV|”.
However, the reference voltage generation circuit 100 is influenced by manufacturing variations in current/voltage characteristics of the depletion type transistor Md and current/voltage characteristics of the enhancement type transistor Me. Thus, as circuits configured such that a highly precise reference voltage can be taken out without being influenced by any manufacturing variations, JP 2002-368107 A and JP 2013-246627 A disclose reference voltage generation circuits using a FET type nonvolatile storage element. The reference voltage generation circuits as disclosed in JP 2002-368107 A and JP 2013-246627 A have substantially the same structure as the reference voltage generation circuit 100 illustrated in FIG. 58, and use nonvolatile storage elements as the depletion type transistor Md and the enhancement type transistor Me. The reference voltage generation circuits disclosed in JP 2002-368107 A and JP 2013-246627 A, respectively, use nonvolatile storage elements of the same kind, and adjust an amount of injection of electric charge into a floating gate included in the nonvolatile storage elements to form a depletion type MOSFET and an enhancement type MOSFET. The nonvolatile storage elements have a control gate and the floating gate, and are adapted to be able to control a threshold voltage Vth by injection and discharge of electrons into the floating gate. Thus, the reference voltage generation circuits enable trimming of the threshold voltage Vth to be performed later even when any manufacturing variation occurs. Accordingly, the reference voltage Vref that is taken out in the reference voltage generation circuits is hardly influenced by manufacturing variations.